The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, the optimization of source/drain regions has become complex. In particular, shaped contact structures in the source and drain regions may be utilized to improve available contact area. However, conventional techniques to clean and prepare the shaped contact structures during integrated circuit manufacture often result in damage to the shaped contact structures, resulting in suboptimal contact and increased contact resistance.
Accordingly, it is desirable to provide methods of forming semiconductor devices with increased surface contact and reduced damage to shaped contact structures in source and drain regions resulting from mask stripping and substrate cleaning. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.